1. Field of the Invention
The present invention relates to convolution code generation, and more particularly to a convolution coder of a digital signal processor which consists of a hardware in the digital signal processor and provides a plurality of convolution codes by a single instruction.
2. Description of the Background Art
Data must be transmitted to a receiving part without any error in transmission and reception of digital data. However, since errors can be made in general during the data transmission and reception, many ways have been proposed and actually used to prevent the errors. These can be referred to as an error correction code technique, which includes a block coding and a convolution coding. The present invention relates to the convolution coding technique, in particular, which has been recently used for cellular phones.
To process digital signals, a digital signal processor (DSP) is exclusively used. The DSP has a function of convolutely coding data and supplying the coded data to a digital data receiving part, to transmit the data without error employing the digital processor which provides numerous functions related to the digital signal processing. Now, the convolution coding performed in a conventional DSP will be described.
Generally, for bit-operation in the DSP there are provided instructions such as arithmetic shift or logical shift, AND, OR, EX-OR (exclusive OR), etc., and also there is provided an instruction for fetching a bit in a single word. Therefore, a convolution coding which is a specific signal processing with respect to an input signal is performed using the above-mentioned instructions for the bit operation supplied by the DSP.
Now, the convolution coding will be described with reference to FIG. 1 which is a conceptional diagram. A convolution code with respect to inputted data x(n) is obtained as shown therein. Since an exclusive unit for such a convolution coding does not physically exist in the DSP, the convolution coding is processed using a plurality of instructions.
As shown therein, the convolution coding process, marked a referential numeral 1, produces a convolution code with respect to the inputted data x(n) using a shift register 2 and exclusive logic elements 3, 4. In FIG. 1 when expressing convolution codes n, k, m, these are assumed to be 2, 1, 5, respectively. Here, n is a code word length, that is, the number of bits which are encoded and outputted by the convolution coding each time step, which is 2 in accordance with the above example, k is a message block length which indicates the number of data inputted by each time step, wherein 1 bit is inputted each time step in the above example, and m is a memory block and indicates the number of shift registers in which the inputted data are stored, as shown in FIG. 1, which is required to use a register having 5 cells. x(n) indicates data inputted from a time step n.
Since the input data x(n) is shifted to the left to the right side of the shift register 2 each time step, a first cell D1, a fourth cell D4 and a fifth cell D5 of first to fifth cells D1-D5 constituting the shift register 2 are exclusively logic-operated by the first exclusive logic element 3, thereby generating a first output G0(n). In addition, a second output G1(n) is generated with respect to the first cell D1, the second cell D2, the fourth cell D4 and the fifth cell D5 by the second exclusive logic element 4. Thus, the above processes can be expressed as follows.
G0(1)=x(n)+x(nxe2x88x923)+x(nxe2x88x924)
G1(1)=x(n)+x(nxe2x88x921)+x(nxe2x88x923)+x(nxe2x88x924)xe2x80x83xe2x80x83(1)
In the above example of the (2, 1, 5) convolution code process, when a single bit is inputted to the shift register 2, a couple of outputs are generated by the exclusive logic operation with respect to a bit value in cells which are selected in the time step or a modular-2 addition. That is, whenever a single bit inputted, 2 bits are outputted.
However, since the instructions for the bit operation provided by the DSP must be used in the convolution coding to the input data stream, a sequential instruction performance is required. In other words, the instructions are used in the digital signal processor, the data stream given by sequential instructions becomes convolutely coded.
First, the bit stream constituting a data stream to be inputted is sequentially stored from a highest bit to a lowest bit in a specific part of a memory word by word. Accordingly, the memory includes, for example, a k number of words. Then, when the number of bits included in a single word is N, considering a general size, as shown in FIG. 1, a following process is required with respect to code each bit through the convolution coding.
That is, each bit is coded by a bit-in-word reading step reading x(n) in a current bit as a currently inputted single bit; a data shifting step performing a shifting operation with previously inputted data; an exclusive-logic operating step operating a 2-input exclusive logic with respect to each bit value included in selected cells of the shift register; and a storing step storing G0, G1 which are the results from the previous step in a memory location, the sequence of the process being accomplished using the instructions of the DSP. Accordingly, since every step of the above process must be performed with respect to the entire data, it can be seen that the four steps must be carried out Kxc3x97N times.
Since each step must be designated in a software, there are required a plurality of instructions. Further, although an assembly instruction is in charge of a single process and the process can be performed in one cycle, at least 10 cycles are needed since there are 5 shift register cells. Thus, there is required an operation volume which needs cycles of at least 10xc3x97Nxc3x97K with respect to the entire input data.
In a commonly used digital signal processor, because an operation by each bit is needed to process the convolution coding, instructions performed by each bit are used but the process of the bit unit operation is not possibly performed in the DSP having a data bus system such as 16, 24 or 32 bits, for example. Although it is possible to process the bit unit operation, the bit unit operation must be repeatedly applied to a data word of a data bus width, that is, a 16, 24, or 32-bit width, as many as the number thereof. The convolution coding process consists of the shifting and the exclusive logic operation appropriate to the process by each bit unit, which are relatively simple operations. However, using read/write, shift, and exclusive logic operation instructions which are to be processed in a word unit of the DSP suitable to process a broad data bus width is not desirable since it can not be effectively utilized in usefulness of resources which are supplied for enabling the above process.
Accordingly, the present invention is directed to a convolution code generator which obviates the problems and disadvantages in the conventional art.
An object of the present invention is to provide a convolution code generator that is implemented in a hardware which is suitable for performing a convolution coding operation of a plurality of bits consisting of input data.
Another object of the present invention is to provide a convolution code generator appropriate for processing a convolution coding by a data bus width unit ill a digital signal processor which is suitable to process a relatively broad data bus width.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a convolution code generator, which generates an (n, k, m) convolution code, wherein n is a code word length, k is a message block length, and m is a memory block, which includes: a temporary data storing means for temporarily storing input data of a word of a predetermined data width consisting of a plurality of bits, the temporary data storing means including cells of a first group corresponding to a word and mxe2x88x921 cells of a second group; and a plurality of exclusive logic operation means selectively connected to the cells of the first and second groups for generating the (n, k, m) convolution code with respect to input bits stored in the cells, wherein a part of data of a previous word is stored in the cells of the second group with respect to a present word stored in the cells of the first group.
To achieve the above objects of the present invention, according to a preferred embodiment of the present invention, there is provided a convolution code generator, which generates a (2, 1, 5) convolution code, wherein 2 is a code word length, 1 is a message block length, and 5 is a memory block, including: a temporary data storing means for temporarily storing input data of a word of a predetermined data width consisting of a plurality of bits, the temporary data storing means including cells of a first group corresponding to a word and 4 cells of a second group; and a plurality of exclusive logic operation means selectively connected to the cells of the first and second groups for generating the (2, 1, 5) convolution code with respect to input bits stored in the cells, wherein a part of data of a previous word is stored in the cells of the second group with respect to a present word stored in the cells of the first group, the plurality of exclusive logic operation means including first to fourth exclusive logic operation means for performing exclusive logic operations of the cells of the first group which are adjacent to each other; an exclusive logic operation means for performing an exclusive logic operation of a cell in which a bit is stored and an output of the fourth exclusive operation means to generate a first convolution code with respect to the bit; and another exclusive logic operation means for performing an exclusive logic operation of outputs of the first and fourth exclusive operation means to generate a second convolution code with respect to the bit.
Further, to achieve the above objects of the present invention, there is provided a digital signal processor for processing a digital input, which includes a memory, an accumulator and a plurality of signal processing units and has a bus connected with the devices for input/output of data, the digital signal processor including: a convolution code generating means for generating an (n, k, m) convolution code wherein n is a code word length, k is a message block length, and m is a memory block and loading the convolution code to the accumulator through the bus, the convolution code generating means including; a convolution code generator having a temporary data storing means for temporarily storing input data of a word of a predetermined data width consisting of a plurality of bits, the temporary data storing means including cells of a first group corresponding to a word and mxe2x88x921 cells of a second group; and a plurality of exclusive logic operation means selectively connected to the cells of the first and second groups for generating the (n, k, m) convolution code with respect to input bits stored in the cells, wherein a part of data of a previous word is stored in the cells of the second group with respect to a present word stored in the cells of the first group.